Rfid integrated circuits with antenna contacts on multiple surfaces

ABSTRACT

Embodiments are directed to a Radio Frequency Identification (RFID) integrated circuit (IC) having a first circuit block electrically coupled to first and second antenna contacts. The first antenna contact is disposed on a first surface of the IC and the second antenna contact is disposed on a second surface of the IC different from the first surface. The first and second antenna contacts are electrically disconnected from each other.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims the benefit of U.S. Provisional PatentApplication Ser. No. 61/623,016 filed on Apr. 11, 2012. The disclosureof the provisional patent application is hereby incorporated byreference in its entirety.

This application claims the benefit of U.S. Provisional PatentApplication Ser. No. 61/681,305 filed on Aug. 9, 2012. The disclosure ofthe provisional patent application is hereby incorporated by referencein its entirety.

This application may be found to be related to U.S. Pat. No. 8,188,927issued on May 29, 2012, the entirety of which is hereby incorporated byreference.

This application may be found to be related to U.S. Pat. No. 8,174,367issued on May 8, 2012, the entirety of which is hereby incorporated byreference.

This application may be found to be related to U.S. Pat. No. 8,228,175issued on Jul. 24, 2012, the entirety of which is hereby incorporated byreference.

This application may be found to be related to U.S. Pat. No. 7,482,251issued on Jan. 27, 2009, the entirety of which is hereby incorporated byreference.

BACKGROUND

Radio-Frequency Identification (RFID) systems typically include RFIDreaders, also known as RFID reader/writers or RFID interrogators, andRFID tags. RFID systems can be used to inventory, locate, identify,authenticate, configure, enable/disable, and monitor items to which thetags are attached or in which the tags are embedded. RFID systems may beused in retail applications to inventory and track items; in consumer-and industrial-electronics applications to configure and monitor items;in security applications to prevent loss or theft of items; inanti-counterfeiting applications to ensure item authenticity; and inmyriad other applications.

RFID systems operate by an RFID reader interrogating one or more tagsusing a Radio Frequency (RF) wave. The RF wave is typicallyelectromagnetic, at least in the far field. The RF wave can also bepredominantly electric or magnetic in the near field. The RF wave mayencode one or more commands that instruct the tags to perform one ormore actions.

A tag that senses the interrogating RF wave may respond by transmittingback a responding RF wave (a response). A tag may generate the responseeither originally, or by reflecting back a portion of the interrogatingRF wave in a process known as backscatter. Backscatter may take place ina number of ways.

The reader receives, demodulates, and decodes the response. The decodedresponse may include data stored in the tag such as a serial number,price, date, time, destination, encrypted message, electronic signature,other data, any combination of tag data, and so on. The decoded responsemay also include status information or attributes about the tag or itemsuch as a tag status message, item status message, configuration data,and so on.

An RFID tag typically includes an antenna and an RFID integrated circuit(IC) comprising a radio section, a power management section, andfrequently a logical section, a memory, or both. In some RFID ICs thelogical section may include a cryptographic algorithm which may rely onone or more passwords or keys stored in tag memory. In earlier RFID tagsthe power management section often used an energy storage device such asa battery. RFID tags with an energy storage device are known asbattery-assisted, semi-active, or active tags. Advances in semiconductortechnology have miniaturized the IC electronics so much that an RFID tagcan be powered solely by the RF signal it receives. Such RFID tags donot include an energy storage device and are called passive tags. Ofcourse, even passive tags typically include temporary energy- anddata/flag-storage elements such as capacitors or inductors.

In typical RFID tags the IC is electrically coupled to the antenna,which in turn is disposed on a substrate. As technology advances and ICsshrink, assembling, aligning, and coupling the IC to the antenna becomeschallenging.

BRIEF SUMMARY

This summary introduces a selection of concepts in a simplified formthat are further described below in the Detailed Description. Thissummary is not intended to identify key features or essential featuresof the claimed subject matter, nor is it intended as an aid indetermining the scope of the claimed subject matter.

An RFID IC is typically electrically coupled to an antenna via two ormore antenna contacts situated on a single surface of the IC, thatcouple to two or more antenna terminals when the IC is assembled ontothe antenna. This coupling may be face-down, by placing the IC face downon the antenna terminals such that the antenna contacts electricallycouple to the terminals. This face-down case involves aligning theantenna contacts with the antenna terminals during assembly and makingan electrical (galvanic, capacitive, or inductive) connection betweenthem. Or it may be face-up, by placing the IC face up on the substrateand attaching bondwires between the antenna contacts and the antennaterminals. This face-up case involves attaching wires from the antennacontacts to the antenna terminals. Because the antenna contacts aresituated on a single surface of the IC, as IC sizes shrink the contactsalso shrink, often both in size (the area of each contact) and spacing(the distance between contacts). This shrinkage increases the cost ofcoupling the antenna contacts to the antenna terminals, in the face-downcase due to alignment tolerances, and in the face-up case due tobondwire attachment tolerances. Both cases involve complicated assemblymachines with consequent high cost. Using an intermediate elementbetween the IC and the antenna, such as a strap or an interposer, doesnot alleviate the problem because the IC-to-strap alignment then becomesthe bottleneck.

Embodiments are directed to placing the antenna contacts on differentsurfaces of the IC, and using antennas and assembly methods thatelectrically couple the antenna terminals to the different surfaces. Forexample, one contact may be disposed on one surface of the IC, andanother contact may be disposed on the opposing surface of the IC. Usingmultiple IC surfaces increases the effective area for, and provides anatural separation between, the antenna contacts. The result issimplified and lower-cost IC-to-antenna assembly.

Embodiments are also directed to an RFID IC having first and secondantenna contacts, and a first circuit block that is electrically coupledbetween them. The first antenna contact is disposed on a first surfaceof the IC and the second antenna contact is disposed on a second surfaceof the IC different from the first. The first and second antennacontacts are electrically disconnected from each other, although in someembodiments the first circuit block may be capable of electricallyconnecting and disconnecting them. Two elements are said to beelectrically connected when a low-impedance electrical path existsbetween them, and are said to be electrically disconnected when no suchlow-impedance path is present. Of course, electrically disconnectedantenna contacts will always have some unavoidable stray capacitive orinductive coupling between them, but the intent of the disconnection isto minimize this stray coupling to a negligible level when compared withan electrically connected path.

Embodiments are further directed to a method of manufacturing an RFIDIC. The method includes forming a first antenna contact on a firstsurface of the IC, forming a second antenna contact on a second surfaceof the IC different from the first, and electrically coupling a firstcircuit block to the first and second antenna contacts.

Embodiments are also directed to a method for generating an RF response(a responding RF wave) from an RFID IC having a first antenna contactdisposed on a first surface of the IC and a second antenna contactdisposed on a second surface of the IC different from the first. Themethod includes providing data to be encoded in the response andelectrically connecting and disconnecting the first and second antennacontacts through an electrically conductive substrate to generate theresponse.

Embodiments are also directed to an RFID tag having an RFID IC with afirst antenna contact disposed on a first surface of the IC and a secondantenna contact disposed on a second surface of the IC different fromthe first. The tag includes a substrate having a first antenna segmentelectrically coupled to the first antenna contact and a second antennasegment electrically coupled to the second antenna contact.

Embodiments are further directed to a portion of an RFID tag includingan RFID IC with a first antenna contact disposed on a first surface ofthe IC, a second antenna contact disposed on a second surface of the ICdifferent from the first, and a layer of conductive material disposed ona surface of a nonconductive material. The first antenna contact iselectrically coupled to the layer of conductive material such that theconductive layer and the second antenna contact form an antenna portconfigured to couple with an antenna.

Embodiments are also directed to a method for fabricating an RFID tag.The method includes dispensing an RFID IC with a first antenna contactdisposed on a first surface of the IC and a second antenna contactdisposed on a second surface of the IC different from the first onto atag substrate such that at least one of the first and second antennacontacts electrically couple to an antenna segment on the substrate.

These and other features and advantages will be apparent from a readingof the following detailed description and a review of the associateddrawings. It is to be understood that both the foregoing generaldescription and the following detailed description are explanatory onlyand are not restrictive of aspects as claimed.

BRIEF DESCRIPTION OF THE DRAWINGS

The following Detailed Description proceeds with reference to theaccompanying Drawings, in which:

FIG. 1 is a block diagram of components of an RFID system.

FIG. 2 is a diagram showing components of a passive RFID tag, such as atag that can be used in the system of FIG. 1.

FIG. 3 is a conceptual diagram for explaining a half-duplex mode ofcommunication between the components of the RFID system of FIG. 1.

FIG. 4 is a block diagram showing a detail of an RFID IC, such as theone shown in FIG. 2.

FIG. 5A and 5B illustrate signal paths during tag-to-reader andreader-to-tag communications in the block diagram of FIG. 4.

FIG. 6 is a conceptual diagram of an IC with antenna contacts on twosurfaces (a dual-sided IC).

FIG. 7 is a conceptual diagram of a dual-sided IC contacting multipleantenna terminals according to embodiments.

FIG. 8 illustrates IC configurations using large antenna contactsaccording to embodiments.

FIGS. 9A-B are top and section views of an RFID IC aligned on asubstrate according to embodiments.

FIGS. 10A-D depict various configurations of dual-sided ICs contactingmultiple antenna terminals according to embodiments.

FIGS. 11A-C depict further configurations of dual-sided ICs contactingmultiple antenna terminals according to embodiments.

FIGS. 12A-C depict various configurations of dual-sided ICs on tagsubstrates according to embodiments.

FIGS. 13A-C depict various methods for dispensing dual-sided ICs ontotag substrates according to embodiments.

FIG. 14 depicts non-square dual-sided ICs according to embodiments.

FIGS. 15A-C depict side cutaway views of dual-sided ICs contactingantenna terminals according to embodiments.

FIGS. 16A-C depict side cutaway views of rectifiers in a dual-sided ICelectrically coupled to antenna contacts on different surfaces of the ICaccording to embodiments.

FIGS. 17 depict stabilization layers used to reduce capacitancevariations between dual-sided ICs and antenna terminals according toembodiments.

FIGS. 18A-C depict side cutaway views of rectifiers in adual-differential dual-sided IC coupling to contacts on differentsurfaces of the IC.

FIGS. 19A-B depict conceptual diagrams of dual-sided IC wafer testsystems.

FIG. 20 is a timing diagram showing commands from an RFID reader andresponses from a population of RFID tags for reading combinations offirst and second codes of the tags according to embodiments.

FIGS. 21A-B illustrate RFID tag front-end equivalent circuits includinga tuning circuit according to embodiments.

FIG. 22 is a flowchart for an RFID tag tuning process according toembodiments.

FIG. 23 is a diagram of RFID tag IC states before and afterself-serialization according to embodiments.

FIG. 24 is a flowchart of a tag IC self-serialization process accordingto embodiments.

FIG. 25 is a block diagram of components of an electrical circuit formedin a tag IC according to embodiments.

FIG. 26 is a conceptual diagram illustrating how the tag can be in oneof different behavior states according to embodiments.

FIG. 27 illustrates switching the exposed tag memory from private topublic states, and vice versa.

FIG. 28 is a diagram showing the effects of a broadcast refresh on tagflag physical parameters as a function of time, according toembodiments.

DETAILED DESCRIPTION

In the following detailed description, references are made to theaccompanying drawings that form a part hereof, and in which are shown byway of illustration specific embodiments or examples. These embodimentsor examples may be combined, other aspects may be utilized, andstructural changes may be made without departing from the spirit orscope of the present disclosure. The following detailed description istherefore not to be taken in a limiting sense, and the scope of thepresent invention is defined by the appended claims and theirequivalents.

FIG. 1 is a diagram showing components of a typical RFID system 100,incorporating embodiments. An RFID reader 110 transmits an interrogatingRF wave 112. RFID tag 120 in the vicinity of reader 110 may senseinterrogating RF wave 112 and generate wave 126 in response. RFID reader110 senses and interprets wave 126.

Reader 110 and tag 120 communicate via waves 112 and 126. Whilecommunicating, each encodes, modulates, and transmits data to the other,and each receives, demodulates, and decodes data from the other. Thedata can be modulated onto, and demodulated from, RF waveforms. The RFwaveforms are typically in a suitable range of frequencies, such asthose near 900 MHz, 13.56 MHz, and so on.

The communication between reader and tag uses symbols, also called RFIDsymbols. A symbol can be a delimiter, a calibration symbol, and so on.Symbols can be implemented for exchanging binary data, such as “0” and“1” if desired. When the symbols are processed internally by reader 110and tag 120 they can be treated as values, numbers, and so on.

Tag 120 can be a passive tag, or an active or battery-assisted tag(i.e., having its own power source). When tag 120 is a passive tag it ispowered from wave 112.

FIG. 2 is a representative diagram of an RFID tag 220, which mayfunction as tag 120 of FIG. 1. Tag 220 is drawn as a passive tag,meaning it does not have its own power source. Much of what is describedin this document, however, also applies to active and battery-assistedtags (including this description of tag 220).

Tag 220 is typically (although not necessarily) formed on asubstantially planar inlay 222, which can be made in many ways known inthe art. Tag 220 includes an electrical circuit which is preferablyimplemented as an integrated circuit (IC) 224. In some embodiments, IC224 may be implemented in complementary metal-oxide semiconductor (CMOS)technology. In other embodiments IC 224 may be implemented in othertechnologies such as bipolar junction transistor (BJT) technology,metal-semiconductor field-effect transistor (MESFET) technology, andothers as will be well known to those skilled in the art. IC 224 isarranged on inlay 222.

Tag 220 also includes an antenna for exchanging wireless signals withits environment. The antenna is often flat and attached to inlay 222. IC224 is electrically coupled to the antenna via suitable antenna contactson IC 224 and antenna terminals on antenna segments 227 (neither thecontacts nor terminals are shown in FIG. 2).

IC 224 is shown with a single antenna port, comprising two antennacontacts electrically coupled to the two antenna segments 227 which areshown here forming a dipole. Many other embodiments are possible usingany number of ports, contacts, antennas, and/or antenna segments.Antenna segments 227 are shown here forming a dipole antenna, but inother embodiments may form only part of an antenna.

In operation, the antenna receives a signal and communicates it to IC224, which both harvests power and responds if appropriate, based on theincoming signal and the IC's internal state. If IC 224 uses backscattermodulation then it responds by modulating the antenna's reflectance,which generates response wave 126 from wave 112 transmitted by thereader. Electrically connecting and disconnecting the antenna contactsof IC 224 can modulate the antenna's reflectance, as can a variety ofother means.

In the embodiment of FIG. 2, antenna segments 227 are separate from IC224. In other embodiments, antenna segments may alternatively be formedon IC 224. Tag antennas according to embodiments may be designed in anyform and are not limited to dipoles. For example, the tag antenna may bea patch, a slot, a loop, a coil, a horn, a spiral, or any other suitableantenna.

The components of the RFID system of FIG. 1 may communicate with eachother in any number of modes. One such mode is called full duplex.Another such mode is called half-duplex, and is described below.

FIG. 3 is a conceptual diagram 300 for explaining the half-duplex modeof communication between the components of the RFID system of FIG. 1,especially when tag 120 is implemented as passive tag 220 of FIG. 2. Theexplanation is made with reference to a TIME axis, and also to a humanmetaphor of “talking” and “listening”. The actual technicalimplementations for “talking” and “listening” are now described.

RFID reader 110 and RFID tag 120 talk and listen to each other by takingturns. As seen on axis TIME, when reader 110 talks to tag 120 thecommunication session is designated as “R→T”, and when tag 120 talks toreader 110 the communication session is designated as “T→R”. Along theTIME axis, a sample R→T communication session occurs during a timeinterval 312, and a following sample T→R communication session occursduring a time interval 326. Of course interval 312 is typically of adifferent duration than interval 326 - here the durations are shownapproximately equal only for purposes of illustration.

According to blocks 332 and 336, RFID reader 110 talks during interval312, and listens during interval 326. According to blocks 342 and 346,RFID tag 120 listens while reader 110 talks (during interval 312), andtalks while reader 110 listens (during interval 326).

In terms of actual technical behavior, during interval 312, reader 110talks to tag 120 as follows. According to block 352, reader 110transmits wave 112, which was first described in reference to FIG. 1. Atthe same time, according to block 362, tag 120 receives wave 112 andprocesses it, to extract data and so on. Meanwhile, according to block372, tag 120 does not backscatter with its antenna, and according toblock 382, reader 110 has no wave to receive from tag 120.

During interval 326, tag 120 talks to reader 110 as follows. Accordingto block 356, reader 110 transmits a Continuous Wave (CW), which can bethought of as a carrier signal that typically encodes no information. Asdiscussed before, this carrier signal serves both to be harvested by tag120 for its own internal power needs, and also as a wave that tag 120can backscatter. Indeed, during interval 326, according to block 366,tag 120 does not receive a signal for processing. Instead, according toblock 376, tag 120 modulates the CW emitted according to block 356, soas to generate backscatter wave 126. Concurrently, according to block386, reader 110 receives backscatter wave 126 and processes it.

FIG. 4 is a block diagram showing a detail of an RFID IC, such as theone shown in FIG. 2. Electrical circuit 424 in FIG. 4 may be formed inan IC of an RFID tag, such as IC 224 of FIG. 2. Circuit 424 has a numberof main components that are described in this document. Circuit 424 mayhave a number of additional components from what is shown and described,or different components, depending on the exact implementation.

Circuit 424 shows two antenna contacts 432, 433, suitable for couplingto antenna segments such as segments 227 of RFID tag 220 of FIG. 2. Whenthe two antenna contacts form the signal input and return from/to anantenna they are often referred-to as an antenna port. Antenna contacts432, 433 may be made in any suitable way, such as from metallic pads andso on. In some embodiments circuit 424 uses more than two antennacontacts, especially when tag 220 has more than one antenna.

Circuit 424 also includes signal-routing section 435 which may includesignal wiring, a receive/transmit switch that can selectively route asignal, and so on.

Circuit 424 also includes a rectifier and PMU (Power Management Unit)441 that harvests energy from the RF wave received by antenna 227 topower the circuits of IC 424 during either or both reader-to-tag (R→T)and tag-to-reader (T→R) sessions. Rectifier and PMU 441 may beimplemented in any way known in the art. In some embodiments,particularly those in which tag 220 includes more than one antenna,rectifier and PMU 441 may include more than one rectifier.

Circuit 424 additionally includes a demodulator 442 that demodulates theRF signal received via antenna contacts 432, 433. Demodulator 442 may beimplemented in any way known in the art, for example including a slicer,amplifier, and so on.

Circuit 424 further includes a processing block 444 that receives theoutput from demodulator 442 and performs operations such as commanddecoding, memory interfacing, and so on. In addition, processing block444 may generate an output signal for transmission. Processing block 444may be implemented in any way known in the art, for example bycombinations of one or more of a processor, memory, decoder, encoder,and so on.

Circuit 424 additionally includes a modulator 446 that modulates anoutput signal generated by processing block 444. The modulated signal istransmitted by driving antenna contacts 432, 433, and therefore drivingthe load presented by the electrically coupled antenna segment orsegments. The term “electrically coupled” as used herein may mean adirect electrical connection, or it may mean a connection that includesone or more intervening circuit blocks, elements, or devices. The“electrical” part of the term “electrically coupled” as used in thisdocument shall mean a coupling that is one or more of ohmic/galvanic,capacitive, and/or inductive. Modulator 446 may be implemented in anyway known in the art, for example including a switch, driver, amplifier,and so on.

In one embodiment, demodulator 442 and modulator 446 may be combined ina single transceiver circuit. In another embodiment modulator 446 maymodulate a signal using backscatter. In another embodiment modulator 446may include an active transmitter. In yet other embodiments demodulator442 and modulator 446 may be part of processing block 444.

Circuit 424 additionally includes a memory 450 to stores data 452. Atleast a portion of memory 450 is preferably implemented as a NonvolatileMemory (NVM), which means that data 452 is retained even when circuit424 does not have power, as is frequently the case for a passive RFIDtag.

In terms of processing a signal, circuit 424 operates differently duringa R→T session and a T→R session. The different operations are describedbelow, in this case with circuit 424 representing an IC of an RFID tag.

FIG. 5A shows version 524-A of components of circuit 424 of FIG. 4,further modified to emphasize a signal operation during a R→T session(receive mode of operation) during time interval 312 of FIG. 3. An RFwave received from antenna contacts 432, 433, is demodulated bydemodulator 442. The demodulated signal is provided to processing block444 as C_IN. In one embodiment, C_IN may include a received stream ofsymbols.

Version 524-A shows as relatively obscured those components that do notplay a part in processing a signal during a R→T session. Rectifier andPMU 441 may be active, but typically only for converting RF power.Modulator 446 generally does not transmit during a R→T session, andtypically does not interact with the received RF wave significantly,either because switching action in section 435 of FIG. 4 disconnectsmodulator 446 from the RF wave, or because modulator 446 is designed tohave a suitable impedance, and so on.

Although modulator 446 is typically inactive during a R→T session, itneed not be so. For example, during a R→T session modulator 446 could beadjusting its own parameters for operation in a future session, and soon.

FIG. 5B shows version 524-B of components of circuit 424 of FIG. 4,further modified to emphasize a signal operation during a T→R sessionduring time interval 326 of FIG. 3. Processing block 444 outputs asignal C_OUT. In one embodiment, C_OUT may include a stream of symbolsfor transmission. C_OUT is then modulated by modulator 446 and providedto antenna segments such as segments 227 of RFID tag 220 via antennacontacts 432, 433.

Version 524-B shows as relatively obscured those components that do notplay a part in processing a signal during a T→R session. Rectifier andPMU 441 may be active, but typically only for converting RF power.Demodulator 442 generally does not receive during a T→R session, andtypically does not interact with the transmitted RF wave significantly,either because switching action in section 435 of FIG. 4 disconnectsdemodulator 442 from the RF wave, or because demodulator 442 is designedto have a suitable impedance, and so on.

Although demodulator 442 is typically inactive during a T→R session, itneed not be so. For example, during a T→R session demodulator 442 couldbe adjusting its own parameters for operation in a future session, andso on.

In typical embodiments, demodulator 442 and modulator 446 are operableto demodulate and modulate signals according to a protocol, such asVersion 1.2.0 of the Class-1 Generation-2 UHF RFID Protocol forCommunications at 860 MHz-960 MHz (“Gen2 Specification”) by EPCglobal,Inc., which is hereby incorporated by reference in its entirety. Inembodiments where electrical circuit 424 includes multiple demodulatorsand/or multiple modulators, each may be configured to support differentprotocols or different sets of protocols. A protocol specifies, in part,how symbols are encoded for communication, and may include modulations,encodings, rates, timings, or any other parameters associated with datacommunications.

Embodiments may also include methods of manufacturing a tag as describedherein. These methods may be performed in conjunction with one or morehuman operators. These human operators need not be collocated with eachother, and each can be with a machine that performs a portion of themanufacturing.

Embodiments for manufacturing a tag as described herein may additionallyinclude programs, and methods of operating the programs. A program isgenerally defined as a group of steps or instructions leading to adesired result, due to the nature of the elements in the steps and theirsequence.

Executing a program's steps or instructions requires manipulatingphysical quantities that represent information. These quantities may beelectrical, magnetic, and electromagnetic charges or particles, statesof matter, and in the more general case the states of any physicalelements. These quantities are often transferred, combined, compared,and processed according to the steps or instructions. It is convenientat times to refer to the information represented by the states of thesequantities as bits, data bits, samples, values, symbols, characters,terms, numbers, or the like. It should be borne in mind, however, thatall of these and similar terms are associated with the appropriatephysical quantities, and that these terms are merely convenient labelsapplied to these physical quantities, individually or in groups.

Executing a program's steps or instructions may further require storagemedia that have stored thereon a program's instructions and/or data,typically in a machine-readable form. This storage media is typicallytermed a memory, read by a processor or other machine element. Inelectronic devices the memory may be implemented as Read Only Memory(ROM), Random Access Memory (RAM), and many others as will be well knownto those skilled in the art. In some embodiments the memory may bevolatile and in others nonvolatile.

Even though it is said that a program is stored in a memory, it shouldbe clear to a person skilled in the art that the program need not residein a single memory, or even be executed by a single machine. Variousportions, modules, data, or features of the program may reside inseparate memories and be executed by separate machines.

Often, for sake of convenience, it is desirable to implement anddescribe a program for manufacturing a tag according to embodiments assoftware. The software can be unitary or can be considered as variousinterconnected software modules.

Embodiments of an RFID tag or of a program for manufacturing an RFID tagas described herein can be implemented as hardware, software, firmware,or any combination thereof It is advantageous to consider such a tag assubdivided into components or modules. A person skilled in the art willrecognize that some of these components or modules can be implemented ashardware, some as software, some as firmware, and some as a combination.

As described above, an RFID tag may be manufactured by placing an RFIDIC (e.g., IC 224 in FIG. 2) on an antenna (e.g., antenna 227) disposedon a substrate (e.g. substrate 222) and electrically coupling contactsof the IC to terminals of the antenna. Conventional antenna contacts aredisposed on a single surface of the IC, and electrically couple to theantenna terminals either by placing the IC face down on the antennaterminals such that the antenna contacts electrically couple to theantenna terminals, or by placing the IC face-up and attaching bondwiresbetween the antenna contacts and the antenna terminals. However, asdescribed above, as IC sizes shrink the corresponding antenna portsbecome smaller, both in terms of contact size and contact spacing. Thisshrinkage increases the cost of coupling the antenna contacts to theantenna terminals, in the face-down case due to tight alignmenttolerances, and in the face-up case due to tight bondwire attachmenttolerances.

Disposing the antenna contacts on different surfaces of the IC addressesthis issue. FIG. 6 is a conceptual diagram of a dual-sided IC 600 withantenna contacts on two different surfaces. In some embodiments IC 600may be an RFID IC as described in relation to FIG. 2, although theconcept is not limited to RFID ICs. Typical ICs have six surfaces (frontsurface 610, back surface 630, and four sides), although ICs withmore-complex shapes may have more or fewer surfaces. In typicalembodiments IC circuitry 660 is disposed in or on one of these surfacesand is electrically coupled to two antenna contacts disposed on any twonon-identical surfaces. FIG. 6 shows a representative embodiment with ICcircuitry on front surface 610, a front-surface contact 620 that couplesdirectly to IC circuitry 660, and a back-surface contact 640 thatcouples to IC circuitry 660 by means of through-IC via 650. In FIG. 6,the front-surface contact 620 is only on the front surface 610 and theback-surface contact 640 is only on the back surface 630. However, insome embodiments, the front-surface contact 620 and/or the back-surfacecontact 640 may be present on multiple surfaces. For example, thefront-surface contact 620 may be on the front surface 610 as well as onthe back-surface 630 and/or any of the other four, unlabeled surfaces.Similarly, the back-surface contact 640 may be present on the backsurface 630 as well as on the front surface 610 and/or any of the otherfour, unlabeled surfaces.

FIG. 7 is a conceptual diagram showing a top view 720 and a side view740 of a dual-sided IC coupled to antenna terminals 702 and 704according to embodiments. The antenna terminals may, in turn, couple toor be part of antenna segments such as segments 227 in FIG. 2, or mayform a strap or interposer suitable for connecting to antenna segments,or in the general case may be any type of precursor that allows IC 600to be attached to an antenna or to another electrical component. In FIG.7, dual-sided IC 706, such as IC 600 described above in relation to FIG.6, is disposed between terminal 702 and an electrical bridge 708 suchthat its front-surface antenna contact (e.g., front-surface contact 620in FIG. 6) is electrically coupled to terminal 702 and its back-surfaceantenna contact (e.g., back-surface contact 640 in FIG. 6) iselectrically coupled to bridge 708. Bridge 708, in turn, electricallycouples to terminal 704. Because IC 706 has front-to-back symmetry, itcan alternatively be sandwiched between terminal 702 and bridge 708 withits back-surface antenna contact electrically coupled to terminal 702and its front-surface antenna contact electrically coupled to bridge708. Indeed, an advantage of the present invention is that in manyembodiments IC 706 may be mounted front-side up or front-side downwithout impacting its operation.

In some embodiments a dielectric layer 710 may be disposed betweenterminal 702 and bridge 708 to prevent an inadvertent short circuitbetween the terminal 702 and bridge 708.

In some embodiments the electrical coupling between the elements in FIG.7 (e.g. between IC 706, terminals 702 and 704, and/or bridge 708) may becapacitive or inductive rather than Ohmic or galvanic and may include adielectric layer disposed between them. For example, a layer ofnon-conductive paste (NCP) or film may be disposed between IC 706 andterminal 702 and/or between IC 706 and bridge 708, and the couplingbetween them may be capacitive.

In some embodiments the front-surface and/or back-surface contacts of IC706 may use one or more large contact pads, as described in U.S. patentapplication Ser. No. 13/456,653 (Attorney Docket No.5088.0113USD1/IMPJ-0436) filed on Apr. 26, 2012, which has beenincorporated by reference in its entirety. FIG. 8 illustrates ICconfigurations 800 and 850 using large contact pads according toembodiments. In IC configuration 800, IC 802 has a single large contactpad 804 that substantially spans a surface of the IC. In ICconfiguration 850, IC 802 has two large contact pads 806 that togetherspan a surface of the IC. Embodiments with more than two large contactpads are possible as well. For clarity, IC configurations 800 and 850show only one IC surface (the top surface), but in embodiments accordingto the present invention multiple surfaces of IC 802 such as the bottomsurface (not visible) or a side surface of IC 802 will also have one ormore contact pads (either small or large). Also, although contact pads804 and 806 are shown in FIG. 8 spanning substantially the entiresurface of IC 802, in other embodiments the contact pads may be smallerand may merely span a reasonable portion of the IC surface.

In other embodiments the contact pads may be shaped or formed in such away as to improve adhesion between the contact pads and the antennaterminals. Examples include but are not limited to providing one or morecavities, slots, or gaps in the center of the contact pad(s) (not shownin FIG. 8) into which an adhesive (such as a conductive epoxy,nonconductive epoxy, contact adhesive, solder, or other similarmaterial) may flow when the dual-sided IC and antenna terminals areassembled together. In this case the cavities or gaps act like groovesin a tire that prevent hydroplaning, but in the case of the presentinvention they provide a path for the adhesive to flow and bond.

In embodiments as disclosed herein, the large contact pads electricallycouple to one or more antenna terminals or bridges (e.g., terminal 702and/or bridge 708 in FIG. 7). Because the contact-pad area is large, theplacement/alignment tolerances between the contact pads and the antennaterminals may be reduced compared to ICs with smaller antenna contacts,facilitating assembly. In some embodiments the contact pads, terminals,and/or bridges may include or be coated by a dielectric material, eithernaturally (such as a naturally-grown or enhanced oxide layer likealuminum oxide) or additively (such as a deposited dielectric). In suchembodiments the coupling between the contact pads and the antennaterminals will typically be capacitive or inductive.

Another way to facilitate placement and alignment between the contactpads and antenna terminals is to use alignment bumps. FIGS. 9A-B showtop (920) and section (930) views of an IC 904, such as dual-sided IC600 of FIG. 6, aligned on a substrate portion 902 by alignment bumpsaccording to embodiments. Substrate portion 902 may be part of an inlay(e.g. inlay 222 of FIG. 2) or a strap (an interposing substrate withinterconnections for coupling to an inlay). When IC 904 is placed onsubstrate 902, alignment bumps 906 guide IC 904 into position. It shouldbe apparent that the substrates of terminal 702 and bridge 708 maycontain alignment bumps (not shown in FIG. 7), thereby facilitatingassembly of dual-sided IC 706's top and bottom antenna contacts toterminal 702 and bridge 708.

In some embodiments an underfill 910 may be applied between substrate902 and IC 904 to strengthen the physical bond and/or improve theelectrical coupling between them. Underfill 910 may be conductive(anisotropic conductive paste/film or any other suitable conductivematerial) or nonconductive (nonconductive paste, film, oxide, or anyother suitable nonconductive material). Raised substrate regions 908 maybe used to contain underfill 910 during assembly. Of course, the shapesof alignment bumps 906 and raised substrate regions 908 depend on theapplication and need not be restricted to small round bumps andelongated raised regions. In some embodiments, raised regions similar toraised substrate regions 908 can be used to guide the alignment of an ICitself, similar to how alignment bumps may be used to guide ICalignment.

FIGS. 10, 11, and 12 depict high-level concepts of coupling andassembling dual-sided ICs to antenna terminals according to embodiments.FIGS. 10A-D depict examples of dual-sided ICs coupling to antennaterminals. FIGS. 11A-C depict examples of assembling dual-sided ICs toantenna terminals. And FIG. 12A-C depict examples of tag substrates thatguide assembly of dual-sided ICs to antenna terminals. In allembodiments the final assembly, including IC, antenna terminal, andsubstrate comprises some form of layered “sandwich” including one ormore layers of a metal such as aluminum or copper or tin, a dielectricsuch as paper or plastic or PET, and a dual-sided IC. The layers may beconnected together by gluing, laminating, self-adherence, or in anyother way as will be well known to those skilled in the art.

FIG. 10A depicts a configuration 1020 of a dual-sided IC 1006 disposedbetween a loop 1002 and a bridge 1008. One antenna contact(front-surface contact 620 or back-surface contact 640 in FIG. 6) of IC1006 couples to a first antenna terminal of loop 1002, and anotherantenna contact of IC 1006 couples with bridge 1008 which, in turn,couples to a second antenna terminal of loop 1002. Loop 1002 may act asa tuning element for IC 1006, may form an antenna, and/or may couple toantenna segments such as segments 227 in FIG. 2.

FIG. 10B depicts a configuration 1030 similar to configuration 1020 inFIG. 10A, the difference being that bridge 1008 now covers a significantportion of loop 1002 to improve the electrical coupling between them. Insome embodiments the electrical coupling between bridge 1008 and loop1002 may be capacitive. In some embodiments a natural dielectric of theantenna terminal material, such as aluminum oxide on an aluminumterminal, may be disposed between bridge 1008 and loop 1002.

FIG. 10C depicts a configuration 1040 where bridge 1008 is itself anantenna terminal The overlap between bridge 1008 and terminal 1002allows them to couple together electrically, thereby completing a looparound IC 1008.

FIG. 10D depicts another configuration 1050 where bridge 1008 is anantenna terminal The overlap between bridge 1008 and antenna terminal1002 allows them to couple together electrically, in this case forming atuning element 1010 which may be a tuning stub, a transmission lineformed from the bridge/substrate/terminal sandwich, or may couple toanother tuning element (not shown in FIG. 10D). In this case tuningelement 1010 is an alternative to the tuning loops in FIGS. 10A, 10B,and 10C.

FIGS. 11A-C depict examples of inlays formed with dual-sided ICsaccording to embodiments.

FIG. 11A shows a configuration 1120 of a tag substrate 1112 partitionedinto a first portion 1116 and a second portion 1118 by a fold line 1110.Tag substrate 1112 may be made from any suitable, foldable material. Tagsubstrate 1112 includes first and second antenna terminals 1102 and 1104disposed on first portion 1116, and a bridge 1108 disposed on secondportion 1118. A dual-sided IC 1106 disposed on first portion 1116couples to first terminal 1102 by a first surface antenna contact of theIC; the second surface antenna contact of IC 1106 is exposed. FIG. 11Aalso shows configuration 1122 of the same tag substrate folded alongfold line 1110. The surfaces of portions 1116 and 1118 come together,causing bridge 1108 to electrically couple to the second surface antennacontact of IC 1106 and second terminal 1104. Of course, IC 1106 couldequivalently be disposed on bridge 1108 prior to folding, in which casethe pre-fold configuration 1120 will appear different but the finalresult (configuration 1122) will be the same.

FIG. 11B depicts a tag configuration 1130 similar to that of FIG. 11A,except that bridge 1108 is disposed on a separate strap 1114. A firstsurface antenna contact of dual-sided IC 1106 is electrically coupled tobridge 1108, such that bridge 1108 and the second surface antennacontact of dual-sided IC 1106 form an antenna port. Strap 1114, whenplaced on tag substrate 1112, couples the antenna port to the terminalson substrate 1112 forming final configuration 1130 with the secondsurface of IC 1006 electrically coupled to terminal 1102 and bridge 1108electrically coupled to terminal 1104. Of course, many alternativeconfigurations are possible, including with IC 1006 initially attachedto terminal 1102, terminal 1104, or bridge 1108. FIG. 11C shows anembodiment with IC 1006 initially attached to terminal 1102.

In all the above embodiments bridge 1108 may be formed on a fold of thetag substrate, on a flap or cutout of the tag substrate, on materialinitially separate from the tag substrate, from a conductive ink,polymer, or layer that is printed, evaporated, or deposited on the tagsubstrate, or in any other fashion as will be obvious to those skilledin the art. In some embodiments, the bridge 1108 may be formed of one ormore bridge precursors that are deposited onto the tag substrate andthen subsequently processed to form the bridge 1108, via the applicationof heat, pressure, or any other suitable processing means. Bridgeprecursors may be easily deposited on the substrate, but requireadditional processing to form an electrical connection to a contact orterminal For example, a bridge precursor may include metallic particlesin an ink that is first deposited and then processed such that themetallic particles form a conductive path. In some embodiments bridge1108 includes a metallic or electrically conductive layer that istransferred and bonded to the tag substrate; in other embodiments bridge1008 and its electrically conductive portion may be formed from two ormore pieces that are bonded together to form the bridge. As noted above,in embodiments as disclosed herein the coupling may be galvanic,capacitive, and/or inductive. Bridge 1008 may be bonded to the tagsubstrate using heat, pressure, adhesive (e.g. epoxy), solder, stitchbonding, welding, or in any other way as will be well known to thoseskilled in the art.

Whereas FIGS. 11A-C depict tag structures where a bridge couples asurface antenna contact of a dual-sided IC to an antenna terminal, someembodiments do not need a bridge. For example, returning to FIG. 11A,second terminal 1104 may be disposed on second tag portion 1118 in placeof bridge 1108 such that when tag substrate 1112 is folded along foldline 1110, second antenna terminal 1104 couples to the exposed surfaceantenna contact of dual-sided IC 1106. Similarly, in FIG. 11B, tag strap1114 may include second terminal 1104 in place of bridge 1108, such thatwhen the strap is disposed on tag substrate 1112 first terminal 1102electrically couples to the exposed surface antenna contact ofdual-sided IC 1106. In some embodiments, the second tag portion 1118 orthe strap 1114 may include a portion of or even the entire tag antennarather than an antenna terminal.

In some embodiments, a tag substrate with antenna terminals may bedesigned to facilitate and direct the placement of a dual-sided IC. FIG.12A depicts a top view (above) and a cross-section view (below) of a tagsubstrate 1204 having a recessed or dimpled region 1206 for guiding thepositioning of a dual-sided IC on substrate 1204. Dimpled region 1206 issized to fit the dual-sided IC, and includes a lower antenna terminal1208. A dual-sided IC 1202 (e.g., dual-sided IC 600 in FIG. 6) can thenbe deposited in the dimpled region 1206 such that a surface antennacontact of IC 1202 (e.g., front-surface contact 620 or back-surfacecontact 640 in FIG. 6) couples to the lower antenna terminal 1208. Afterthe IC 1202 is deposited in dimpled region 1206, a bridge 1210 can bedeposited on top of IC 1202 to couple another surface antenna contact ofIC 1202 to a second antenna terminal Whereas in FIG. 12A, bridge 1210 isdepicted as orthogonal to lower antenna terminal 1208, this need not bethe case. For example, bridge 1210 may be in-line with lower antennaterminal 1208 (i.e., bridge 1210 may extend to the left instead of tothe top in the top view of the substrate), or may extend in any suitabledirection (e.g., to top, bottom, at any angle, or any other suitabledirection including out of the plane of tag substrate 1204).

In some embodiments, one or more apertures 1212 may be formed in thebottom of dimpled region 1206 and may be used for placing andpositioning the IC 1202, as described below in relation to FIG. 13A.Preferably, aperture(s) 1212 are smaller than IC 1202, such that IC 1202cannot pass through. However, aperture(s) 1212 may provide sufficientarea for fluids (i.e., liquids or gases or adhesives or solder) to passthrough.

In some embodiments, a hole in the tag substrate may direct the placingand positioning of a dual-sided IC. This through-substrate hole may beused instead of or in addition to a dimpled region. FIG. 12B depicts atop view (above) and a cross-section view (below) of a tag substrate1224 having a hole 1226 sized to fit a dual-sided IC 1222. In contrastto dimpled region 1206 of tag substrate 1204 described above, hole 1226passes completely through tag substrate 1224. To prevent IC 1222 fromfalling completely through hole 1226, and for coupling to one of IC1222's surface antenna contacts, tag substrate 1224 includes a lowerantenna terminal 1228 disposed on one side of tag substrate 1224, whichsubstantially occludes hole 1226 and together with hole 1226 forms apocket for IC 1222. When IC 1222 is deposited within hole 1226, asurface antenna contact of IC 1222 (e.g., front-surface contact 620 orback-surface contact 640 in FIG. 6) couples to lower antenna terminal1228. Subsequently, a bridge 1230 may be disposed above IC 1222 tocouple another antenna terminal to the other surface antenna contact ofIC 1222. Similar to the description for FIG. 12A, bridge 1230 can extendin any suitable direction, including as a sheet that extends in alldirections around IC 1222. Likewise, lower antenna terminal 1228 mayextend in any direction or may be a sheet. In some embodiments, one ormore apertures 1232 similar to aperture(s) 1212 in FIG. 12A may beformed in lower antenna terminal 1228 to aid in placing and positioningIC 1222.

Whereas dimpled region 1206 in FIG. 12A and hole 1226 in FIG. 12B areshown as square, they need not be so. For example, dimpled region 1206and/or hole 1226 may be rectangular, circular, elliptical, hexagonal, orof any suitable convex or concave shape. In some embodiments, dimpledregion 1206/hole 1226 are sufficiently large to fit an entire IC, but inother embodiments, dimpled region 1206/hole 1226 may only be largeenough to accommodate a portion of an IC.

FIG. 12C depicts another method to couple a dual-sided IC's surfacecontacts to antenna terminals on a substrate according to embodiments.Diagram 1240 depicts a top view (above) and a cross-section view (below)of a tag substrate 1244 having a first antenna terminal 1248 and asecond antenna terminal 1250. A slot 1246 cut into tag substrate 1244separates first antenna terminal 1248 and second antenna terminal 1250.A dual-sided IC 1242 is placed within slot 1246 such that one surfacecontact of IC 1242 couples to first antenna terminal 1248 and anothersurface contact of IC 1242 couples to second antenna terminal 1250. Slot1246, which is shown inclined with respect to the plane of substrate1244, may be inclined as any angle, or may even be orthogonal to theplane of tag substrate 1244 (i.e., downward in the cross-section view).In some embodiments the terminals may be fabricated as a singleterminal, then slot 1246 cut through this single terminal to separate itinto two antenna terminals 1248 and 1250. In some embodiments, slot 1246may be cut entirely through substrate 1244, instead of only through aportion as shown in the cross-section view. In some embodiments one ormore apertures (not shown) may be formed between the bottom of slot 1246and the bottom of tag substrate 1244 for IC placement and positioning.

Using a dual-sided IC simplifies tag assembly. Because a dual-sided IChas surface contacts on opposing sides, either side can be placed onto atag substrate. In addition, because a dual-sided IC typically hassurface contacts on its largest sides, a dual-sided IC can simply bedropped onto a tag substrate and in most cases land with a surfacecontact facing the tag substrate. Therefore, the IC does not necessarilyhave to be maintained in a particular position or orientation beforeassembly, thus allowing simpler, more cost-effective assembly methods.For example, instead of having to be individually picked and placed ontotag substrates, as conventional ICs do, dual-sided ICs can be handledand dispensed in bulk, as described below. However, dual-sided ICs maystill be compatible with conventional pick-and-place techniques.

FIG. 13A depicts a method for dispensing dual-sided ICs onto tagsubstrates (such as those described in FIGS. 12A-C) according toembodiments. Diagram 1300 depicts a bulk IC dispenser 1306 containingmultiple dual-sided ICs 1304. Note that the orientation and positioningof the ICs 1304 within bulk dispenser 1306 does not need to be strictlycontrolled. In some embodiments, of course, the orientation of ICs 1304may be controlled to some degree in order to streamline the dispensingprocess.

Bulk IC dispenser 1306 dispenses ICs 1304 onto a web of tag substrates1302, which in some embodiments may be similar to tag substrates 1204,1224, and 1244 in FIGS. 12A-C. In some embodiments, the dispensingprocess may also position the dispensed ICs into desired locations onthe tag substrates 1302. For example, the IC dispenser 1306 may bepositioned over a desired IC location (e.g., dimpled region 1206 in FIG.12A, hole 1226 in FIG. 12B, or slot 1246 in FIG. 12C), and an IC 1304 isdispensed into a desired location by gravity (i.e., dropped) or placedby a machine.

As will be obvious to those skilled in the art, there are manytechniques for aligning dispensed ICs to their proper locations on asubstrate, whether the substrate includes dimples/holes/slots as inFIGS. 12A-C or is planar as in FIGS. 10A-D or FIGS. 11A-C. One way, asdescribed above, involves using gravity to place the ICs in theirdesired locations. Another way uses a magnet positioned below the tagsubstrate to attract magnetic ICs to their desired locations. Yetanother way uses electric charge on the tag substrate to draw chargedICs to their desired locations. FIG. 13B depicts a representative method1310 for using electric charge to position dual-sided ICs ontosubstrates according to embodiments. In method 1310, a laser 1312induces charge of a particular polarity at a desired target location1314 on substrate 1302. Subsequently, bulk IC dispenser 1306 dispensesICs 1304 charged with a different polarity, which are attracted by thecharged targets 1314 to their proper location on substrate 1302, shownschematically by inlay 1316. While a laser is used to induce charge inFIG. 13B, in other embodiments other methods may be used to generatecharge on the substrate. In some embodiments topological features (e.g.,bumps 906) may help position the ICs.

Other ways to align dispensed ICs to their proper locations on asubstrate include using vibration or fluid flow to move an IC to apotential well (i.e., a substrate location with lower potential energythan other substrate locations), where the well can have lowgravitational potential, electric potential, magnetic potential, orsimilar. For example, a tag substrate with an IC placed near a dimpledregion or hole may be vibrated such that the IC moves into the dimpledregion or hole but does not escape once there. Similarly, fluid or gasflow may convey a dispensed IC across a substrate until it falls into arecessed location (e.g., dimpled region 1206, hole 1226, or slot 1246 inFIGS. 12A-C, respectively). As another example, a fluid or gas that isdrawn from the top side of the substrate to the back side through anaperture at the desired location (e.g., aperture(s) 1222 or 1232 inFIGS. 12A or 12B, respectively) may draw an IC to the desired locationand hold it there for subsequent processing.

In some embodiments, applying a pressure differential between the twosides of a tag substrate will achieve the desired fluid/gas flow throughapertures in the substrate. FIG. 13C depicts a method 1320 for using apressure differential, specifically a vacuum, to position dual-sided ICson tag substrates. In method 1320, vacuum 1324 is applied to the backside of substrate 1302 containing at least one through-substrateaperture 1322 (e.g., aperture(s) 1222 or 1232 in FIGS. 12A-B).Subsequently, when ICs 1304 are brought near the front side of substrate1302 one of the loose ICs 1304 is pulled to the substrate by the vacuum1324 acting through aperture 1322, resulting in inlay 1328. Method 1320is self-limiting, because once vacuum 1324 pulls a single IC 1304 to theaperture 1322, aperture 1322 is then blocked by the IC 1304 and nofurther ICs will be drawn to that aperture. If the same vacuum source isused for multiple substrates and/or multiple apertures, then as eachaperture attracts a blocking IC, the vacuum through the remainingapertures will become stronger, thus accelerating the placement process.In some embodiments, electrostatic or magnetic forces (e.g., asdescribed above in FIG. 13B) or topological features (e.g., bumps 906)may also be used to help position the IC. Finally, in some embodimentsthe pressure differential may be applied from the front side of the tagsubstrate, where front-side pressure can be used to push ICs intoposition over apertures, rather than back-side vacuum pulling them intoposition.

In other embodiments, fluid surface tension can be used to position ICson a substrate. For example, one or more drops of fluid may be placed ata desired location on the substrate. When the IC is dispensed onto thesubstrate, it may be drawn to the fluid droplets as a result of surfacetension. In some embodiments, solder may be deposited on the substrate(e.g., via screen-printing) and then heated to form the fluid droplets.Solder may also (or instead) be deposited on one or more surfaces of theIC. When heated, the solder on the IC may melt to form droplets that arepreferentially attracted to metallic antenna leads on a substrate.

Although all the dual-sided ICs depicted herein have been square,dual-sided ICs may have other shapes as well. FIG. 14 depicts twoexamples of non-square ICs. IC 1402 has an octagonal shape, and IC 1404has a hexagonal shape. Non-rectangular ICs may benefit from lessinternal stress, resulting in improved reliability, and may also lacksharp corners that are susceptible to damage during bulk handling or theIC-dispensing methods described above. Non-rectangular ICs may befabricated via, for example, etching processes such as those describedin U.S. Pat. No. 7,482,251 issued on Jan. 27, 2009, the entirety ofwhich has been incorporated by reference.

FIGS. 15A-C depict side cutaway views of dual-sided ICs electricallycoupling to antenna terminals according to embodiments.

FIG. 15A depicts a side cutaway view 1500 of a dual-sided IC 1506similar to dual-sided ICs 600, 706, 1006, 1106, 1202, and 1222 describedabove. Dual-sided IC 1506 includes circuitry 1508 disposed in or on itsfront surface (shown facing downward). Circuitry 1508 is electricallycoupled to antenna terminal 1504 by means of its front-surface antennacontact 1514. Dual-sided IC 1506 also includes a back-surface antennacontact 1516 that may couple to circuitry 1508 by a number ofmethods—FIG. 15A shows one method which involves a through-IC via. Insome embodiments the through-IC via may be electrically connected tosubstrate 1510; in other embodiments it may be electrically disconnectedfrom substrate 1510; in yet other embodiments it may not be present atall. In the embodiment of FIG. 15A back-surface antenna contact 1516,which couples to antenna terminal 1502, is shown electricallydisconnected from substrate 1510 by an optional dielectric layer 1518.Of course, back-surface antenna contact 1516 may be electricallyconnected to substrate 1510 as well. In some embodiments, optional bumps1520 and/or 1522 may improve the coupling between the antenna contactsand the antenna terminals.

FIG. 15B depicts a side cutaway view 1530 of a dual-sided IC 1532similar to IC 1506 in FIG. 15A. Like IC 1506, IC 1532 includes circuitry1508 disposed in or on its front surface that is electrically coupled toterminal 1504 by means of a front-surface antenna contact 1514. UnlikeFIG. 15A, IC 1532 does not include a through-IC via; instead, circuitry1508 couples to terminal 1502 through substrate 1510. When IC 1532receives an RF signal across front-surface antenna contact 1514 andback-surface antenna contact 1516, the electrical potential differenceacross IC 1532 causes current to flow from front-surface antenna contact1514 to back-surface antenna contact 1516 through substrate 1510, and/orvice-versa. Substrate 1510 is typically conductive, but in somecircumstances it may be insulating and the current flow from front toback surface may be through the capacitance of insulating substrate1510. In other embodiments substrate 1510 may exhibit an inductance. InFIG. 15B, substrate 1510 forms the back-surface antenna contact; inother embodiments the back surface may include a metallic orsemi-metallic layer (as in FIG. 8) or may be doped to have a highelectrical conductivity. FIG. 15B also shows an optional dielectriclayer 1518 separating the back surface of IC 1532 from terminal 1502, sothe coupling between them is capacitive, but of course a galvaniccoupling is possible as well. Dielectric 1518 may be deposited onsubstrate 1510 or may be a naturally occurring oxide of substrate 1510such as SiO2. Similarly, front-surface antenna contact 1514 maycapacitively couple with terminal 1504 through an optional dielectriclayer 1534 or it may galvanically couple. The ordering of dielectriclayer 1534 and front-surface antenna contact 1514 may be swapped, sothat dielectric layer 1534 is disposed on circuitry 1508 andfront-surface antenna contact 1514 is disposed between dielectric layer1534 and terminal 1504.

FIG. 15C depicts a side cutaway view 1540 of a dual-sided IC 1542similar to IC 1532 in FIG. 15B. Like with IC 1532, IC 1542 includescircuitry 1508 disposed in or on its front surface, an optionalfront-surface dielectric layer 1544, a front-surface antenna contact1514, a galvanically or capacitively coupled substrate 1510, an optionalback-surface dielectric layer 1518 and a back-surface antenna contact1516. Unlike FIG. 15B, circuitry 1508 couples to front-surface antennacontact 1514 by means of one or more primary contacts 1546 throughdielectric layer 1544. Also unlike FIG. 15B, dielectric layer 1518 maybe present on one or more side surfaces of IC 1542. Back-surface antennacontact 1516 may couple to a side contact 1550 that spans at least oneside of IC 1542 and couples with circuitry 1508 by means of secondarycontacts 1548 through dielectric layer 1518. Essentially, side contact1550 forms a conductive or galvanic path from circuitry 1508 toback-surface contact 1518 that is an alternative to the through-IC viain FIG. 15A. In some embodiments circuitry 1508 may couple capacitivelywith side contact 1550 rather than through secondary contacts 1548. Inother embodiments dielectric 1544 does not cover one or more of thefront, side, or back surfaces of IC 1542.

Dielectric layer 1518 may be a native oxide that forms on substrate 1510or may be deposited on IC 1542. The oxide formation or deposition mayoccur at any time. Similarly, side contact 1550 may be a region ofsubstrate 1510 doped for a conductivity that is higher than that of thenative substrate 1510 or may be deposited on substrate 1510. The dopingor deposition may occur at any time.

FIGS. 16A-C depict side cutaway views of dual-sided ICs with at leastone circuit element electrically coupled to contacts on at least twosurfaces of the IC according to embodiments. FIG. 16 shows the circuitelement as a rectifier, but the element could be any circuit componentsuch as those described in reference to FIG. 4. In some embodiments therectifier may be a charge pump - this disclosure uses the terms“rectifier” and “charge pump” interchangeably. Rectifiers as describedherein couple to antennas, so in a dual-sided ICs they couple to the twoantenna contacts on different surfaces of the IC. FIG. 16A depicts adual-sided IC 1600 similar to dual-sided ICs 1506/described in referenceto FIG. 15. Dual-sided IC 1600 includes, as part of circuitry 1602, arectifier 1604 that is electrically coupled to front-surface antennacontact 1606 and to back-surface antenna contact 1614 by a through-ICvia 1610. Like for IC 1506, a dielectric layer 1612 may optionallyseparate back-surface antenna contact 1614 from IC substrate 1608.

FIG. 16B depicts another dual-sided IC 1620, similar to dual-sided IC1600 described in reference to FIG. 16A. The difference in FIG. 16B isthat rectifier 1604 couples with back-surface antenna contact 1614 bymeans of substrate 1608 instead of by a through-IC via, shownschematically by back-surface antenna contact 1614 and rectifierterminal 1616 being grounded (i.e. back-surface antenna contact 1614 andrectifier terminal 1616 are electrically coupled through a conductivesubstrate at a common potential). Of course, the reference to ground asused herein means only a common potential and need not convey anyconnection with earth ground. In some embodiments the substrate may bemade conductive by doping; in other embodiments circuitry 1602 may befabricated on an epitaxial layer of substrate 1608 that is eitherelectrically connected to or disconnected from conductive substrate1608. In the latter case rectifier terminal 1616 may couple to substrate1608 capacitively.

FIG. 16C depicts another dual-sided IC 1640, similar to dual-sided IC1620 described in reference to FIG. 16B. In IC 1640, circuitry 1602 alsoincludes a modulator 1642 that is electrically coupled to front-surfaceantenna contact 1606 and back-surface antenna contact 1614. Modulator1642 couples with back-surface antenna contact 1614 through substrate1608, similar to rectifier 1604. When IC 1640 responds by backscattering(as described above in reference to FIG. 2), modulator 1642 may modulatethe impedance (or admittance) between front-surface antenna contact 1606and back-surface antenna contact 1614 in order to modify the currentflowing through substrate 1608 (as described above in relation to FIG.15B) and thereby generate the response. The total impedance between thetwo surface antenna contacts depends on the impedance of rectifier 1604,modulator 1642, and substrate 1608. By modulating its own impedancebased on a desired reply signal, modulator 1642 alters the totalimpedance between the two surface antenna contacts and thereby modulatesthe currents flowing through substrate 1608. As a specific butnot-limiting example, modulator 1642 may electrically connect anddisconnect (via switching action) the two surface antenna contacts togenerate the response signal.

FIGS. 16A, 16B, and 16C should not be construed as limiting the types orelements of circuitry 1602 that may couple across multiple surfaces of adual-sided IC. As will be described below, other circuits that maysimilarly couple include modulators, PMUs, antenna-routing nodes,impedance matching circuits, ESD circuits, and indeed any circuitrypresent in an RFID IC.

In some embodiments dielectric 1518/1534/1544 may be or may include anonconductive stabilization layer. The stabilization layer may aid inmitigating mounting capacitance variations due to varying mountingforces.

Diagram 1700 shows an RFID strap or inlay comprising substrate 1720 andantenna terminal 1727 being pressed against RFID IC 1724 with a mountingforce F1 (1702), where antenna terminal 1727 and antenna contact 1712are separated from the IC by stabilization layer 1710. Mounting distanceD1 (1704) is fixed by stabilization layer 1710, producing a similarlyfixed mounting capacitance C1.

Diagram 1750 shows the RFID strap or inlay being pressed against theRFID IC with a mounting force F2 (1752) which is larger than mountingforce F1. The presence of stabilization layer 1710 ensures that mountingdistance D2 (1754) is substantially the same as mounting distance D1(1704) despite the larger mounting force F2. As a result, mountingcapacitance C2 is substantially similar to mounting capacitance C1,helping ensure that the tags have similar tuning and therefore similarperformance characteristics.

In some embodiments, bumps formed through openings in stabilizationlayer 1710 electrically connect circuits 1762 to antenna contact 1712.Stabilization layer 1710 may be an organic or inorganic material,typically (although not necessarily) with a relatively low dielectricconstant and a reasonable thickness to provide small capacitance. Ananisotropic conductive adhesive, patterned conductive adhesive, ornonconductive adhesive 1713 may optionally be applied between the IC andthe strap/inlay to attach the IC to the strap/inlay, either or bothphysically and electrically. If adhesive layer 1713 is nonconductivethen it is typically sufficiently thin that at the frequencies of RFIDcommunications it provides a low-impedance capacitive path betweenantenna terminal 1727 and antenna contact 1712.

In some embodiments antenna contact 1712, similar to contact pads 804 or806 in FIG. 8, substantially covers the surface of RFID IC 1724. Forreasons of clarity, FIG. 17 does not show the back-surface antennacontact such as contact 1614 in FIG. 16. It should be apparent that thisback-surface antenna contact may be formed with or without astabilization layer, independent or whether the IC front surfaceincludes a stabilization layer, and that this back surface stabilizationlayer can be or can include the dielectric layer 1612 in FIG. 16.

FIGS. 18A-C depict side cutaway views of rectifiers in dual-differentialdual-sided ICs coupling to contacts on multiple surfaces of the IC.Dual-differential RFID ICs contain two or more electrically isolatedantenna ports, in which an odd-mode excitation on one antenna portproduces essentially no excitation on another antenna port.

Dual-differential ICs typically include multiple rectifiers, eachelectrically coupled to a different antenna port. FIG. 18A depicts afirst dual-differential dual-sided IC 1800 including circuitry 1802having a first rectifier 1804 and a second rectifier 1806. Firstrectifier 1804 is electrically coupled to a first front-surface antennacontact 1808, and second rectifier 1806 is electrically coupled to asecond front-surface antenna contact 1810. Both rectifiers couple to aback-surface antenna contact 1822 through substrate 1812, similar todual-sided IC 1620 described in FIG. 16B. Like with FIG. 16B, thereference to ground means only a common potential and need not conveyany connection with earth ground.

FIG. 18B depicts a second dual-differential dual-sided IC 1830 includingcircuitry 1802 having a first rectifier 1804 and a second rectifier1806. IC 1830 is similar to IC 1800 described in reference to FIG. 18A,but IC 1830 includes two back-surface contacts with first rectifier 1804coupling to back-surface antenna contact 1822 by means of substrate 1812and second rectifier 1806 coupling to back-surface antenna contact 1826by a through-die via 1824 which is typically electrically disconnectedfrom substrate 1812 by a dielectric layer 1828.

FIG. 18C depicts a third dual-differential dual-sided IC 1860 includingcircuitry 1802 having a first rectifier 1804 and a second rectifier1806. IC 1860 is similar to IC 1830 described in reference to FIG. 18B,but IC 1860 includes two through-IC vias with first rectifier 1804coupling to back-surface antenna contact 1822 by through-die via 1834and second rectifier 1806 coupling to back-surface antenna contact 1826by through-die via 1824. Typically at least one, and often both, ofthese through-IC vias are electrically disconnected from substrate 1812by a dielectric layer 1828.

Dual-sided ICs may enable other applications in addition to facilitatingantenna pad alignment to antenna terminals. As one example, dual-sidedICs on a semiconductor wafer may facilitate wafer-scale testing. FIGS.19A-B depict conceptual diagrams of a dual-sided IC wafer test systemaccording to embodiments.

FIG. 19A depicts a wafer test system 1900 for testing a dual-sided ICwafer 1902 which includes one or more dual-sided ICs as described above.The cross-sectional portion of wafer 1902 depicts three dual-sided ICs,only one of which is labeled (IC 1908). IC 1908 includes IC circuitry(not shown) coupled to a front-surface contact 1906 and to aback-surface contact 1918 through one of the means described above(e.g., a through-wafer via, substrate coupling, etc.). A probe card 1910couples test bus 1914 to multiple probe contacts 1912 which are often,but not necessarily, electrically disconnected from each other (in RFIDsystems, where RFID ICs contain singulation algorithms, the probecontacts 1912 need not be disconnected at all). A second test lead 1916is electrically coupled to back-surface contact 1920 which in FIG. 19Aspans multiple die (and in some embodiments may span the entire wafer).During wafer testing, probe card 1910 is positioned such that each probecontact 1912 couples galvanically or capacitively to an IC front-surfacecontact (e.g., front-surface contact 1906). By providing a test signalto test bus 1914 and test lead 1916, multiple dual-sided ICs on thewafer 1902 may be simultaneously tested. As suggested by FIG. 19A, thelarge size of the front-side IC contacts and the fact that the secondtest lead couples to back-surface contact 1918 reduces the alignmenttolerances required by probe-card 1910.

FIG. 19B depicts another wafer test system 1950 for testing a dual-sidedIC wafer 1902. Instead of a probe card with individual probe contactsthat couple to the IC front-surface contacts, test-system 1950 uses aflexible, conductive contact layer 1920 to perform the coupling. Becausethe entire contact layer 1920 is conductive, wafer test system 1950eliminates the alignment requirements for probe-to-IC-contact. Flexiblecontact layer 1920 may be a flexible and/or conformable material that iselectrically conductive, such as a conductive rubber or polymer. Tocouple flexible contact layer 1920 to the IC front-surface contacts, aforce or pressure (such as might be applied by a gas, fluid, or othermeans) may be applied to the back of contact layer 1920 and/or to theback of wafer 1902. Alternatively, a high-dielectric-constant orconductive gas or fluid may be placed between flexible contact layer1920 and wafer 1904 to facilitate capacitive or galvanic coupling,respectively, between them.

In some embodiments back-surface contact 1918 may include a conductivemetallic or semi-metallic layer such metal, polysilicon, and/or a dopedlayer that allows second test lead 1916 to make a galvanic connection.In other embodiments back-surface contact 1918 may include a dielectricor insulating layer that allows second test lead 1916 to make acapacitive connection.

Dual-sided ICs as described herein may implement any functionalityavailable to a single-sided IC, but with the many advantages andbenefits described in this document. Although some of thesefunctionalities are described below, it should be apparent to oneskilled in the art that dual-sided ICs may implement functionalities notexplicitly described herein.

In some embodiments, a dual-sided IC may be configured to backscatter acombination of codes, as described in U.S. Pat. No. 8,174,367 issued onMay 8, 2012, which has been incorporated by reference. FIG. 20 is atiming diagram 2000 showing commands from an RFID reader and replies bya population of RFID tags according to embodiments. Neither the readernor the tags are shown in diagram 2000. In some embodiments, the tagsmay store a first code and a second code. The commands in diagram 2000cause tags to ^(“)gush” a reply comprising combinations of first andsecond codes, without any intervening reader commands between them,according to embodiments.

Timing diagram 2000 proceeds downward along a vertical axis TIME, withcommands 2012 transmitted by the reader alternating with replies 2026from the tags. In the example of diagram 2000, the reader firstinstructs the tags to gush their replies by means of one or more of anoptional ENABLE GUSH command 2002 and a GUSH command 2003. During thetime each tag is singulated the reader has a transaction with thesingulated tag and receives tag data. Three example transactions 2030,2040, 2050 are described, but more or less such transactions may takeplace. Each transaction 2030, 2040, 2050 is not necessarily described infull, but only some pertinent commands are given. Not shown arecommands, for example, to singulate each tag for its transaction.Finally, an optional DISABLE GUSH command may terminate the gushingbehavior.

In first transaction 2030 with a first singulated tag, command CMD3 2005causes the first tag to send a reply comprising a combination 2035 of atleast a portion of codel and at least a portion of code2 from tagmemory, without the tag receiving a reader command in-between sendingthe two code portions. In transaction 2040 with a second singulated tag,a repeated command CMD3 2005 elicits a combination 2045 from the secondtag, again with no intervening command. Then in transaction 2050 with athird singulated tag, a repeated command CMD3 2005 elicits a combination2055 from the third tag, again with no intervening command

In some embodiments transactions 2030, 2040, and 2050 may take less timethan transactions that involve sending the first and second codesseparately, with an intervening reader command in between.

In some embodiments, a dual-sided IC may be configured with a tuningcircuit to match antenna and IC impedances for facilitating powerextraction from an incident RF wave. FIG. 21A illustrates an RFID tagfront-end equivalent circuit 2100 including a tuning circuit and amemory for storing tuning data, according to one embodiment. The RFIDtag front-end equivalent circuit 2100 models the various impedances ofan RFID tag and includes an antenna section 2108, an IC input section2110, and a matching network that couples the antenna section 2108 tothe IC input section 2110. The antenna section 2108 includes inductor2104 and capacitor 2106, which model the reactive portion of the antennaimpedance, and resistor 2102, which models the real portion of theantenna impedance. The IC input section 2110 includes a resistor 2112that models the input resistance of the IC, and a capacitor 2114 thatmodels the input reactance of the IC. The matching network includes aninductor 2116 that models the inductance of the matching network.

The equivalent circuit 2100 also includes a tuning circuit 2120electrically coupled to a variable impedance element 2122. The tuningcircuit 2120 may include an optional nonvolatile memory (NVM) 2124electrically coupled to a processing block 2126. NVM 2124, which isconfigured to store and maintain data even in the absence of power, mayinclude one or more of ROM, EEPROM, flash, MRAM, FRAM, fuses, or othermemory types known in the art for storing data, and may beone-time-programmable or may be able to be written to and/or erasedrepeatedly. NVM 2124 stores information about the tag tuning, such assettings for variable impedance element 2122. These settings may bepreprogrammed into the NVM before or after the RFID IC is integratedinto an RFID tag.

In some embodiments the settings stored in NVM 2124 may be dynamicallyadjusted. For example, in the course of a tag-tuning process (e.g.,process 2200 described below in relation to FIG. 22) the storedvariable-impedance settings may be overwritten or supplemented by newsettings that provide better impedance matching.

NVM 2124 may also store data about the power extracted and/or reflectedby the tag. For example, NVM 2124 may store previous values of extractedand/or reflected power for use in an iterative tag-tuning process, wheresuccessively detected values of extracted/reflected power are used toevaluate the effect of variable-impedance adjustments.

In some embodiments NVM 2124 is not required, in which case processingblock 2126 may use or cycle through preset or algorithmically determinedvalues for variable impedance element 2122 to improve the powerextraction.

Processing block 2126 is typically configured to adjust variableimpedance element 2122 to increase the amount of power that IC 424extracts from an RF wave incident on the tag antenna. Processing block2126 may adjust variable impedance element 2122 based on impedancesettings stored in NVM 2124, based on previous extracted/reflected powerdata stored in NVM 2124, and/or based on one or moreimpedance-adjustment algorithms. Processing block 2126 may also updateor overwrite the stored impedance settings if new settings provide moreextracted RF power. In some embodiments processing block 2126 may adjustthe impedance upon command from an external entity (e.g., an RFIDreader). In other embodiments processing block 2126 may also (orinstead) adjust the impedance based on one or more environmentalconditions.

FIG. 21B illustrates another RFID tag front-end equivalent circuit 2150including a tuning circuit 2120, according to embodiments. In circuit2150, tuning circuit 2120 may be configured to determine an amount ofextracted power and to adjust variable impedance element 2122 based onthe amount. In one embodiment, a power detector 2152, which may beintegrated into tuning circuit 2120 or into another circuit in IC 424(e.g., in a rectifier or PMU), detects the amount of RF power extractedby the IC from the tag antenna (e.g. tag antenna 227 in FIG. 2). In oneexample, power detector 2152 may simply be the supply voltage developedby IC 424 from the RF wave incident on the tag antenna.

A tuning controller 2156 may adjust variable impedance element 2122 toimprove the impedance match and thereby increase the extracted power. Acomparator 2154 determines whether the extracted power is increasing ordecreasing as the tuning controller adjusts the variable impedanceelement, thereby allowing the tuning controller to determine how toalter the impedance value to improve power transfer.

In some embodiments, the tuning circuit 2120 may be configured tooperate at lower extracted power levels than IC 424. In someembodiments, a rectifier or PMU may disable IC 424 until the tuningcircuit has maximized the extracted power and/or the amount of extractedpower is sufficient to operate IC 424.

FIG. 22 is a flowchart for an RFID tag tuning process 2200 according toembodiments. Tuning process 2200 begins with step 2210, where an RFIDtag with an antenna, an IC, a variable impedance element, and a tuningcircuit extracts power from an incident RF wave at a level exceeding a“sufficient power to tune” (SPTT) parameter. In some instances theextracted power will be less than a “sufficient power to operate IC”(SPOT) parameter, in which case the tag IC will not have sufficientpower to operate according to a protocol. However, tuning circuit 2120does operate, because the extracted power is greater than the SPTT. Inoptional step 2220, the variable impedance element resets to an initialstate. In some instances tuning circuit 2120 may set the initial statevia a tuning algorithm, or retrieve the initial state from a memory(e.g., NVM 2124 in FIG. 21A) and apply it to the variable impedanceelement, or may use the variable impedance element's previous state asthe initial state. In other instances the variable impedance elementwill set or reset itself to the initial state.

In step 2230, the tuning circuit samples the power extracted by the RFIDtag, either to determine a baseline value (at the beginning of thetuning process) or to evaluate the effect of an impedance change (duringthe tuning process). If the latter then the tuning circuit in step 2240determines if the newly sampled power value is less than one or morepreviously sampled power values. If not then the tuning continues. If sothen the tuning circuit may assume that the power transfer andextraction has been maximized, and the process then moves to step 2280where the tuning circuit halts the adjustment process. In someembodiments the criterion for determining whether the impedance valuehas been optimized may be complex, especially in cases where therelationship between the variable impedance element and the extractedpower is not monotonic. In such circumstances the tuning circuit may usea search algorithm (in some cases including techniques available tothose versed in computer science and/or machine learning) to determineif the power transfer can be improved further, even if the newly sampledpower value is less than prior samples.

If the newly sampled power value exceeds the previously sampled value(s)or if the tuning circuit determines that power transfer can be furtherimproved then the tuning circuit determines a new variable impedancevalue in step 2250. The tuning circuit may determine the impedance valuein a variety of ways, such as using fixed steps, binary tree-traversal,proportional to the prior improvement, or using another algorithm aswill be well known to those skilled in the engineering discipline. Thenew impedance value will, in general, be based on the most recentsampled power value (and in some embodiments, multiple previous powersamples). In step 2260 the tuning circuit may optionally check if thenew impedance value exceeds the tuning range of the variable impedancerange. If so then the tuning circuit may halt the tuning process at step2280.

If the new impedance value does not exceed the variable-impedance tuningrange then the tuning circuit adjusts the variable impedance element instep 2270. The tuning process then loops back to step 2230, where a newsample of the extracted power is taken to evaluate the effect of thenewly adjusted impedance. The tuning process 2200 iterates through steps2230-2270 until the extracted power in step 2240 reaches either asufficient value or a maximum (implying the impedance match isoptimized) or until further impedance adjustments would exceed thetuning range of the variable impedance element (i.e. step 2260).

At the conclusion of tuning process 2200, in step 2280, the finalvariable impedance settings may be stored in a tag memory (e.g., in NVM2124 in FIG. 21A). In some embodiments an RFID reader may be able toread the final impedance settings from the memory or instruct the tag ICto send them to the reader.

In some embodiments, both the extracted power and the reflected powermay be sampled in step 2230 and used in the determination of step 2240.In these embodiments, increases in extracted power coupled withdecreases in reflected power correspond to improved power transfer. Theadditional information provided by the reflected power may be useful,for example, in cases where the RFID tag is moving with respect to theRF power source and therefore the incident power is changing. By itself,an increase in extracted power after an impedance adjustment may resultfrom a tag moving closer to a power source and not from better powertransfer. However, by measuring both extracted and reflected power thetuning circuit can determine if the increase in extracted power is dueto tag motion or to the impedance adjustment.

In some embodiments, a dual-sided IC may be configured to self-generatea portion of an identifier in response to a reader signal. FIG. 23 is adiagram 2300 of RFID tag states before and after a self-serializationprocess according to embodiments. An RFID tag attached to an item maystore in volatile or nonvolatile memory a tag serial number (TSN) 2310and an item serial number (ISN) 2320. The TSN 2310 is a number that maybe unique, may be used to identify the tag IC, and may be written intoIC memory during IC manufacturing. Each tag IC in an operatingenvironment preferably has a different TSN 2310 so that individual tagICs can be differentiated from each other. The ISN 2320 is a numberstored on the tag that identifies the item to which the tag is attached.ISN 2320 may be written at or around the time that the tag is associatedwith its host item. Each item in an operating environment preferably hasa different ISN 2320 so that individual items can be differentiated fromeach other. As one example, TSN 2310 may include a tag identifier (TID)and ISN 2320 may include an electronic product code (EPC), a universalproduct code (UPC), or a stock-keeping unit (SKU) number.

The TSN 2310 may be subdivided into at least a tag class identifier(TCI) 2312, which may denote the IC class or type and may be common tomultiple ICs, and a tag instance identifier (TII) 2314 which istypically unique (at least for a period of time) and identifies aparticular IC in the IC class by its serialization. In some instances,for example ones in which tags with different TCIs are not mixed, TCI2312 may be null. In other instances each IC class, make, or model mayhave a different TCI 2312, and all tags of that class, make, or modelmay share the same TCI 2312. TII 2314 allows differentiating individualtags within that class, make, or model from each other. The tag or theIC manufacturer may store TCI 2312 and TII 2314 on the tag at the timeof IC manufacture or soon after.

The ISN 2320 may be at least subdivided into an item class identifier(ICI) 2322, which identifies the class of item to which the tag isattached and may be common to multiple items, and an item instanceidentifier (III) 2324 which may be null, unwritten, or invalid (asindicated by braces [ ] in FIG. 23) until serialized from TSN 2310. III2324, once serialized as III 2326, is typically unique (at least for aperiod of time) and identifies an item in the class by itsserialization. In some instances, for example ones in which tags withdifferent ICIs are not mixed, ICI 2322 may be null. In other instanceseach item class may have a different ICI 2322, and all items of thatclass share the same ICI 2322. III 2326 allows differentiatingparticular items within that item class from each other. For example,ICI 2322 may identify an item class such as diapers and III 2326 mayidentify a particular box of diapers.

In some embodiments, ICI 2322 and III 2326 may be written at or aroundthe time that the tag is associated with its host item. A systemintegrator or end-user may generate ISN 2320, store it on the tag, andapply the tag to its host item. Generating an ISN from scratch mayinvolve a number-management system to generate, assign, and keep trackof the assigned ISNs, particularly because each III should preferably beunique. Ensuring III uniqueness across multiple factories thatmanufacture the same type of item, and across multiple retailers whenthey need to replace a lost or damaged tag and generate a new III for anitem, is a daunting task even if the uniqueness need be guaranteed onlyfor a period of time, because that time period is typically measured inat least weeks, and more often months or years.

In a system according to embodiments, a tag may self-generate its IIIfrom its TSN. In some embodiments a tag may self-generate the III uponexpiration of a timer, automatically upon IC power-up, in response to areader command, automatically prior to backscattering the ISN to areader, or upon a tag processing block performing an operation that usesthe ISN. In some embodiments multiple tags can be instructed tosimultaneously self-generate their Ills. In some instances, if an IIIbecomes corrupted then a reader can instruct a tag to regenerate the IIIfrom the TSN. In some instances a tag stores the self-generated III inNVM. In other instances the tag may store the self-generated III involatile memory and generate it at power-up, upon reader command, orautomatically prior to replying. In some instances the tag may not storethe III at all and may instead self-generate it from the TSN every timeit needs to use or send the III. Regardless of the method, because thetags themselves perform the serialization, the need for expensive ISNmanagement systems is reduced.

In FIG. 23, a tag that has not yet been serialized is in state 0 (2302)in which TSN 2310 (comprising TCI 2312 and TII 2314) has been stored inthe IC. However, the ISN 2320 is incomplete. In some embodiments, a tagin state 0 has ICI 2322 stored in the IC, but not III 2324 which may benull, unwritten, may contain an “unserialized” code, or may be in anyother unprogrammed state as will be obvious to those skilled in the art.In some embodiments a tag also stores a state bit 2306 whose valueindicates the tag state (i.e., whether the ISN has been serialized).

Upon a triggering event, which may be a reader command, a tag power-up,a timer expiration, a processing block 444 event, a request for or aneed to backscatter an ISN, a need to calculate a cyclic redundancycheck (CRC) over the ISN, a need to encrypt the ISN, receiving a signalfrom a reader, or any other event that requires the tag to possess aserialized ISN, a tag in state 0 transitions to state 1 (2304). In state1, TSN 2310 and ICI 2322 remain unchanged relative to state 0, but thetag self-generates III 2326 by applying a function 2330 to at least aportion of TSN 2310. Function 2330 may be as simple as a direct copy(i.e., copy a portion of TSN 2310 into III 2326), an indexed copy (i.e.copy starting at a pointer location), or may include a complex algorithmfor deriving or determining an III from TSN 2310. In some embodimentsfunction 2330 may derive III 2326 from TII 2314. In other embodimentsfunction 2330 may derive III 2326 from the entire TSN 2310. Theself-serialization may also cause the tag to assert state bit 2306 toindicate that the tag's ISN has been serialized.

FIG. 24 is a flowchart of a tag self-serialization process 2400according to embodiments. In step 2410 an RFID tag receives a commandcontaining at least a portion of an ICI. In response, at step 2420, thetag writes an ICI to tag memory. At step 2430 the tag optionallyreceives a signal, either from the same reader as in step 2410 or from adifferent reader. In some embodiments this signal may be a serializecommand instructing the tag to self-generate and store an III. In otherembodiments this signal may be an inventory command or a read commandfor which the tag generates an III with which to respond. In yet otherembodiments this signal may be RF power, such as a CW wave, to which thetag IC powers-up and self-generates an III to use while the tag ispowered. In yet other embodiments this signal may cause the tag togenerate a new III different from a prior III, which may make trackingthe tag difficult so as to protect consumer privacy.

In step 2440 the tag generates an III by applying an algorithm orfunction to at least a portion of a TSN already stored on the tag. Thegeneration may be in response to the command in step 2410, the signal instep 2430, or in response to another trigger event altogether. Thealgorithm or function may be wholly or partially included in the commandor signal, or may be already known to the tag IC. In optional step 2450the tag writes the generated III to volatile or nonvolatile tag memory.This write step is optional because in some instances the tag maygenerate the III in step 2440, transmit it in step 2470 (see below), andthen discard it.

In optional step 2460 the tag locks the memory containing the ICI, III,or both, to prevent subsequent overwriting. Finally, in step 2470 thetag transmits the ISN containing the ICI and the self-generated III to areader, either in response to the command in step 2410, the signal instep 2430, or responsive to another event altogether.

In some embodiments, a dual-sided IC may be configured to exhibitdifferent behaviors or expose different memory portions in differentsituations, as described in U.S. Pat. No. 8,228,175 issued on Jul. 24,2012, which has been incorporated by reference. FIG. 25 is a blockdiagram of components 2524 of an electrical circuit formed in an RFID ICaccording to embodiments. It will be recognized that some of components2524 correspond to analogous components in circuit 424. Components 2524include antenna contacts 2532, 2533, similar to antenna contacts 432,433, for coupling to an antenna. Only two antenna contacts 2532, 2533are shown, but more are possible, etc.

Components 2524 additionally include a memory 2550, analogous to memory450. Memory 2550 may include a Memory Section A 2551, and a MemorySection B 2558. Memory Section A 2551 has a first set of memory bits,and Memory Section B 2558 has a second set of memory bits. It should bekept in mind that, in the embodiment of FIG. 25, Memory Section A 2551is shown as wholly distinct from Memory Section B 2558, but that is onlyin the example of FIG. 25. While Memory Section A 2551 does not itselfcoincide exactly with Memory Section B 2558, the two could have portionsthat overlap, or one could be a subset of the other.

The first set of memory bits in Memory Section A 2551 stores Data A2561, and the second set of memory bits in Memory Section B 2558 storesData B 2568. Again, Data A 2561 is shown as wholly distinct from Data B2568, but that is only in the example of FIG. 25. Some of Data A 2561could be shared with Data B 2568, if any of the respective memory bitsare shared. And, even if not shared, some of Data A 2561 could beidentical with some of Data B 2568.

Components 2524 moreover include a processing block 2544 made accordingto embodiments. Processing block 2544 can be electrically coupled to thetag antenna via antenna contacts 2532, 2533. As such, processing block2544 can receive via the antenna commands that have been issued by anRFID reader, and can operate in conformance with these commands, asspecified according to a communication protocol. Such protocols havebeen described above. Some of these protocols define protocol states forthe tag, and accordingly for processing block 2544.

Often such protocols require a tag to send a specific response to afirst interrogator command, if the tag is in an internal tag protocolstate that is compatible with a certain one of the called-for protocolstates. In some embodiments, processing block 2544 can indeed be capableof being in an internal tag protocol state that is compatible with thecertain called-for protocol state. In some embodiments, processing block2544 can be capable of implementing the present invention with a singleinternal tag protocol state, which can be compatible by being a statethat backscatters an ISN such as an EPC (such as an ISN in FIG. 23). Inother embodiments, processing block 2544 can also be capable ofattaining additional protocol states. Implementation-wise, if there aresuch additional protocol states, processing block 2544 can have aprotocol state machine to point to which internal tag protocol state theprocessing block is in. Whereas microscopically, processing block 2544can be in one or another internal tag protocol state, macroscopically itcan be said that the RFID IC or the whole RFID tag is in this or thatprotocol state.

Often the protocol requires a tag receiving a first interrogator commandto send a specific code in response, if the tag is in a state compatiblewith a certain one of the called-for protocol states. Processing block2544, or its host tag, can start by being in such a compatible state, orit can start from a different state and then transition to thecompatible state. Transitioning can be performed in any number of ways.In some embodiments, transitioning can happen in response to receivingone or more preliminary commands, etc. In fact, a number of protocolsrequire such transitioning, and specify how it is to take place. Oftenthis transitioning is performed as part of the tag becoming singulatedfrom other tags.

If processing block 2544 is in a state compatible with the called-forprotocol state, it may be able to send a reply code as the specificcode, in response to the first command. Sending the reply code can be inconformance with the protocol. A protocol state has been calledcompatible for purposes of this document, in that the reply code is sentwith such conformance, whether it is merely a compatible protocol stateor the exact protocol state.

Processing block 2544 can additionally map either the first set ofmemory bits that are part of Memory Section A 2551 or, alternatively,the second set of memory bits that are part of Memory Section B 2558. Ifprocessing block 2544 maps the first set of memory bits in MemorySection A 2551, which stores the first data, then the reply code can bea first code that is derived at least in part from the mapped firstdata. Alternatively, if processing block 2544 maps the second set bitsin Memory Section B 2558, which stores the second data, then the replycode can be a second code. The second code, derived at least in partfrom the mapped second data, is often different from the first code.

It will be further understood that, while only two memory sections 2551,2558 are shown among components 2524, the invention is not so limited.For example, there could a third memory section, with a third set ofmemory bits, for storing third data. A processing block according tosome embodiments can map the third set of memory bits instead of thefirst or second, such that, if the processing block were to receive thefirst interrogator command while in a state compatible with a called-forprotocol state, the reply code could be a third code derived at least inpart from the third data, and different from the first code and thesecond code.

In general, an IC made according to embodiments optionally also includesa behavior indicator. If provided, the behavior indicator may indicatewhich of the first set and the second set of memory bits is being mappedby the processing block. In the example of FIG. 25, components 2524additionally include an optional behavior indicator 2570. If provided,behavior indicator 2570 indicates either the first set of memory bits inMemory Section A 2551, or the second set of memory bits in MemorySection B 2558. Accordingly, behavior indicator 2570, if provided,further indicates either Data A 2561, or Data B 2568.

A behavior indicator is not required explicitly by the invention. Insome embodiments, the behavior state is indicated instead by thecontext.

If provided, behavior indicator 2570 can be implemented in any number ofways. In some embodiments, but not necessarily all, the behaviorindicator is encoded in one or more values stored in respective one ormore memory cells of the IC. This situation is depicted in FIG. 25 byshowing optional behavior indicator 2570 as straddling the boundary oftag memory 2550. If the behavior indicator is indeed encoded in one ormore memory values then these values can even be values of the firstdata, the second data, etc.

FIG. 26 is a conceptual diagram 2600 illustrating how a tag can be inone of several different behavior states. Behavior state 2610 is abehavior state where the tag is easily readable. Behavior state 2682 isan obscured/privacy/scrambled behavior state, in that its code isscrambled, making it harder to read by an unauthorized reader. Behaviorstate 2684 is an obscured/privacy quiet behavior state, in that willrespond only to a reader whose signal is strong enough. In this state2684 the tag will respond when the reader is nearby, but not when thereader is farther away, even though in both cases the reader signal mayconvey sufficient power for the tag to respond. And a tag in behaviorstate 2686 replies with a scrambled code only to a reader whose signalis strong enough. In some embodiments a tag can even reply from behaviorstate 2610 when the tag is nearby the reader and receiving a strongsignal, but can automatically transition to one of behavior states 2682,2684, 2686 when the tag is far from the reader and receiving a weaksignal.

In some embodiments, a dual-sided IC may be configured to transitionbetween a private profile and a public profile. FIG. 27 illustratesswitching the exposed tag memory from private to public, and vice versa,according to embodiments.

Diagram 2700 shows the transition between private profile 2710 andpublic profile 2720, where different portions of tag memory are hiddenfrom or visible to a reader. In the private profile the tag exposes usermemory; TID memory containing a tag model number, tag serial number, anda public EPC; and EPC memory containing a private EPC. In someapplications a reader writes a value into a public EPC memory locationand then “publicizes” the tag using a QT command. Readers are free toencode as little or as much information into the public EPC field asthey choose (including no information at all) before publicizing thetag.

One usage model for private and public profiles includes a tagcontaining a private EPC in private EPC memory that indicates the itemto which the tag is attached. At point-of-sale a reader may write saleinformation, such as a store code or a sale code, into the public EPClocation located in TID memory, then issue a QT command to switch thetag's exposed memory profile from private to public. Once switched, thetag conceals its user memory, TID serial number, and private EPC.Instead the tag exposes its public EPC in public EPC memory, remappedfrom the prior location in TID memory. During inventory, the tag willnow send this public EPC to a reader, which may contain the sale codebut typically not the EPC of the item to which the tag is attached.Notice that in this example the tag's public memory is a subset of thetag's private memory - the tag remaps its model number and public EPCfrom the private-state TID memory bank to a model number and public EPClocated in the public-state TID and public-state EPC memory banks,respectively. Of course, the public memory need not be a subset of theprivate memory, but could be totally different, as could the choice ofmemory locations to transfer from private state to public. Finally, insome embodiments the state switching is reversible, allowing the readerto instruct the tag to switch from exposing its private memory backagain to exposing its public memory.

In some embodiments, a dual-sided IC may be configured to perform atag-flag refresh. FIG. 28 is a diagram 2800 showing the effects of arefresh on a tag-flag physical parameter as a function of time,according to embodiments. A tag-flag physical parameter may include oneor more of voltage, current, charge, and flux. In some embodiments, ifthe value of a flag physical parameter is above a threshold 2802 thenthe flag is considered to hold a first value (for example, the value“B”), whereas if the value of the flag physical parameter is below thethreshold 2802 then the flag is considered to hold a second value (e.g.,the value “A”). When a tag is subject to an inventory operation 2806then the tag-flag physical parameter may be adjusted so as to switch theflag's value. Although the inventory operation 2806 in FIG. 28 assertsthe tag flag value from “A” to “B”, in other embodiments an inventoryoperation may assert the tag flag value from “B” to “A”. The amount bywhich the tag-flag physical parameter is adjusted by an inventoryoperation may be static (e.g., it is always increased/decreased by apreset amount) or dynamic (e.g., the amount of increase/decrease variesaccording to any number of parameters), as long as the adjustment amountis sufficient to change the flag value.

After the inventory operation 2806, the tag-flag physical parameter willdecay over time, as indicated by curve 2804. At some time 2808 thetag-flag physical parameter will decay below threshold 2802, switchingthe flag value from B back to A. The difference between time 2808 andtime 2806 is the flag's persistence time, and is how long the flag holdsthe value B. The rate at which the physical parameter decays may be afunction of one or more tag and/or environmental conditions, such as tagdesign or temperature.

If the tag is capable of executing a tag-flag refresh, and a readersends a refresh command 2812 such that the tag receives it before time2808 (and therefore before the physical parameter has decayed belowthreshold 2802), then the refresh command 2812 adjusts (or instructs thetag to adjust) the physical parameter to increase the persistence timeof the asserted flag value (in the example of FIG. 28 the asserted valueis “B”). In some embodiments the refresh command 2812 is a broadcastcommand, where the term “broadcast” as used in this document impliesthat the command is directed to a plurality of tags rather than to asingulated tag (where “singulated” is defined as an individual tagsingled-out by a reader from among the plurality of tags). As above, theadjustment amount may be static or dynamic, as long as the post-refreshparameter value is different from the parameter value before the refreshcommand. By broadcasting successive refresh commands (e.g., refreshcommand 2814) the resulting decay curve 2810 can be adjusted such thatthe effective flag persistence time (i.e., the time at which the curve2810 drops below the threshold 2802) can be extended as far beyond thenormal flag persistence time as desired.

According to some embodiments, an RFID IC may include a first circuitblock electrically coupled to first and second antenna contacts. Thefirst antenna contact may be disposed on a first surface of the IC andthe second antenna contact may be disposed on a second surface of the ICdifferent from the first surface. The first and second antenna contactsmay be electrically disconnected from each other.

In some embodiments, the first circuit block may include a rectifier orcharge pump, a modulator, a demodulator, a power management unit, animpedance-matching circuit, and/or a tuning circuit. The first circuitblock may be configured to generate an RF response using half-duplexcommunications. If the first circuit block includes a modulator then themodulator may be configured to electrically connect and disconnect thefirst and second antenna contacts so as to generate an RF reply signal.In some embodiments a reader illuminates the RFID tag with a continuous(i.e. unmodulated) RF wave; the tag modulator connecting anddisconnecting its antenna contacts changes the antenna reflectance andthereby generates a backscattered RF reply signal. The modulator mayelectrically couple to one of the antenna contacts through anelectrically-conductive substrate, by means of a through-IC via, and/orby means of a side contact.

In some embodiments at least one of the first antenna contact and thesecond antenna contact includes at least one conductive pad spanningsubstantially the entire respective surface of the IC. In someembodiments at least a portion of the first antenna contact and thesecond antenna contact is suitable for coupling to an antenna terminalIn some embodiments the first and second antenna contacts couple to thefirst circuit block. In some embodiments the coupling between at leastone of the antenna contacts and the first circuit block is through asubstrate of the IC, a through-IC via, and/or a side contact. In someembodiments the coupling between the first and/or second antennacontacts and its respective antenna terminal may be galvanic orcapacitive. If the coupling is galvanic then the first antenna contactmay include a conductive metallic (e.g., including aluminum, copper,gold, or any other suitable metal) or semimetallic (e.g., including oneor more semi-metals) layer annealed to or deposited on the substrate.The through-IC via may be electrically connected to or electricallydisconnected from the substrate. The side contact may be deposited on athird surface of the IC different from the first and second surfaces.The first circuit block and the first antenna contact may beelectrically connected to each other by a through-IC via and the firstantenna contact as well as the through-IC via may be electricallydisconnected from the substrate.

In some embodiments the IC may include a memory for storing a first codeand a second code, and the first circuit block may include a processingblock operable to cause the first code to be backscattered if a firstcommand is received from an RFID reader, receive a second command, andcause to be backscattered responsive to receiving the second command acombination made from at least portions of the first code and the secondcode, without receiving any commands while the combination is beingbackscattered. The first circuit block may be configured to extractpower with a first efficiency from an RF wave incident on an antenna andbegin operating according to a protocol when the extracted power exceedsa first value, and may include a variable impedance element electricallycoupled to the first and second antenna contacts and a tuning circuitconfigured to begin operating when the extracted power exceeds a secondvalue less than the first value and adjust the variable impedanceelement to enable the first circuit block to extract power from the RFwave with a second efficiency greater than the first efficiency.

In other embodiments the IC may include at least one capacitor couplingat least one of the first and second antenna contacts to an antennaterminal In some embodiments the at least one capacitor contains adielectric material including at least one of a covering layer of the ICand a covering layer of the antenna. The first circuit block may includea processing block configured to receive a refresh signal and refresh aninventoried flag in response to receiving the refresh signal.

According to other examples, a method for manufacturing an RFID IC mayinclude forming a first antenna contact on a first surface of the IC,forming a second antenna contact on a second, different surface of theIC, and coupling a first circuit block in the IC to the first antennacontact and the second antenna contact, where the first and secondantenna contacts are electrically disconnected from each other.

In some embodiments, the first circuit block may include a modulator,and the method may include coupling the modulator to the first antennacontact through a conductive substrate so as to enable the modulator togenerate an RF signal by electrically connecting and disconnecting thefirst and second antenna contacts.

In some embodiments the method may include annealing a conductive layerto or depositing a conductive layer on the substrate. The method mayinclude electrically connecting a through-IC via to, or disconnecting athough-IC via from, the substrate. The method may include annealing ordepositing a side contact on a third surface of the IC different fromthe first and second surfaces, and/or electro-plating the first antennacontact, second antenna contact, and side contact on their respectivesurfaces.

According to further examples, a method for generating a radio-frequency(RF) signal with an RFID IC having a first antenna contact disposed on afirst surface and a second antenna contact disposed on a differentsurface may include providing data to be encoded into the RF signal andelectrically connecting and disconnecting the first and second antennacontacts through a conductive substrate so as to generate the RF signal.

According to some examples, an RFID tag may include an RFID IC with afirst antenna terminal disposed on a first side and a second antennaterminal disposed on a second side different from the first, a first tagportion including a first antenna section electrically coupled to thefirst antenna terminal, and a second tag portion including a secondantenna section electrically coupled to the second antenna terminal.

According to other examples, an RFID strap may include a nonconductivelayer, a conductive layer disposed on a surface of the nonconductivelayer, and an RFID IC with a first antenna terminal disposed on a firstside and a second antenna terminal disposed on a second side differentfrom the first side. The first antenna terminal may be affixed andelectrically coupled to the conductive layer, and the conductive layerand the second antenna terminal may form an antenna port configured tocouple with an RFID antenna.

The above specification, examples, and data provide a completedescription of the composition, manufacture, and use of the embodiments.Although the subject matter has been described in language specific tostructural features and/or methodological acts, it is to be understoodthat the subject matter defined in the appended claims is notnecessarily limited to the specific features or acts described above.Rather, the specific features and acts described above are disclosed asexample forms of implementing the claims and embodiments.

1-90. (canceled)
 91. A method of manufacturing a Radio FrequencyIdentification (RFID) tag, comprising: disposing, onto a first portionof a substrate of the RFID tag, a dual-sided integrated circuit (IC)having a first antenna contact on a first external surface of the IC anda second antenna contact on a second external surface of the ICdifferent from the first external surface of the IC; forming anelectrical connection between the first antenna contact and a firstantenna terminal of the RFID tag; and folding a second portion of thesubstrate onto the first portion of the substrate so as to form anelectrical connection between the second antenna contact and a secondantenna terminal of the RFID tag.
 92. The method of claim 91, furthercomprising: disposing the first antenna terminal on the first portion ofthe tag substrate; and disposing the second antenna terminal on thefirst portion of the t substrate, wherein the second portion of themsubstrate includes an electrical bridge.
 93. The method of claim 91,further comprising disposing the second antenna terminal on the secondportion of the tag substrate.
 94. The method of claim 91, furthercomprising providing at least one of a dimple, a through-substrate hole,and a slot configured to at least partially contain the IC.
 95. Themethod of claim 91, further comprising: providing a through-substratehole in the tag substrate, and disposing the first antenna terminal on aback side of the tag substrate, such that the through-substrate hole andthe first antenna terminal form a pocket for the IC.
 96. The method ofclaim 91, further comprising providing at least one raised region on thetag substrate for guiding the positioning of the IC.
 97. A method ofmanufacturing a Radio Frequency Identification (RFID) tag, comprising:disposing, onto a first substrate of the RFID tag, a dual-sidedintegrated circuit (IC) having a first antenna contact on a firstexternal surface of the IC and a second antenna contact on a secondexternal surface of the IC different from the first external surface ofthe IC; forming an electrical connection between the first antennacontact and a first antenna terminal of the RFID tag; and disposing asecond tag substrate onto the first tag substrate so as to form anelectrical connection between the second antenna contact and a secondantenna terminal of the RFID tag.
 98. The method of claim 97, furthercomprising disposing the second antenna terminal on the first tagsubstrate, wherein the second tag substrate includes an electricalbridge.
 99. The method of claim 97, further comprising disposing thesecond antenna terminal on the second tag substrate.
 100. The method ofclaim 97, further comprising providing at least one of a dimple, athrough-substrate hole, and a slot configured to at least partiallycontain the IC.
 101. The method of claim 97, further comprising:providing a through-substrate hole in the first tag substrate, anddisposing the first antenna terminal on a back side of the first tagsubstrate; wherein the through-substrate hole and the first antennaterminal form a pocket for the IC.
 102. The method of claim 97, furthercomprising providing at least one raised region on the first tagsubstrate for guiding the positioning of the IC.
 103. A method ofmanufacturing a Radio Frequency Identification (RFID) tag, comprising:disposing, onto a substrate of the RFID tag, a dual-sided integratedcircuit (IC) having a first antenna contact on a first external surfaceof the IC and a second antenna contact on a second external surface ofthe IC different from the first external surface of the IC; forming anelectrical connection between the first antenna contact and a firstantenna terminal of the RFID tag; and depositing, on the tag substrate,a bridge that forms an electrical connection between the second antennacontact and a second antenna terminal of the RFID tag.
 104. The methodof claim 103, wherein depositing the bridge includes at least one ofprinting the bridge onto the second antenna contact and depositing abridge precursor onto the second antenna contact.
 105. The method ofclaim 103, further comprising processing the deposited bridge byapplying at least one of heat and pressure to the deposited bridge. 106.The method of claim 103, further comprising providing at least one of adimple, a through-substrate hole, and a slot configured to at leastpartially contain the IC.
 107. The method of claim 103, furthercomprising: providing a through-substrate hole in the tag substrate, anddisposing the first antenna terminal on a back side of the tagsubstrate; wherein the through-substrate hole and the first antennaterminal form a pocket for the IC.
 108. The method of claim 103, furthercomprising providing at least one raised region on the tag substrate forguiding the positioning of the IC.